High bandwidth PLL loops are usually built as type I PLLs, which inherently feature faster loop dynamics. A type I PLL uses only one integrating pole due to the voltage-controlled-oscillator (VCO) frequency-to-phase conversion and, consequently, there is no filtering of the phase error signal. This is important if fast frequency/phase acquisition is required. However, unlike in type II PLL loops, where the steady-state phase error goes to zero in the face of a constant frequency offset (i.e., frequency deviation between the actual and center VCO frequencies), the phase error in type I PLL loops is proportional to the frequency offset. This effectively limits the dynamic range of the phase detector or the maximum operational frequency range of the VCO (or of a digitally-controlled oscillator, DCO) in a type I PLL. This dynamic-range limitation problem is also extended to higher-order digital PLL loops. The loop filter (LF), normally containing an integrating capacitor in analog PLL implementations or an integrator in digital PLL implementations, outputs a “filtered phase error” signal which is roughly proportional to the frequency offset. A need thus exists in the art for a PLL loop that provides for fast frequency/phase acquisition, while minimizing the impact to the dynamic range or the maximum range of a VCO/DCO operational frequency.